Versal VCK190 ACAP

doi:doi:10.57702/32iyy9cr

You're currently viewing an old version of this dataset. To see the current version, click here.

Versal VCK190 ACAP

The dataset used in the paper is the Versal VCK190 ACAP, which is a heterogeneous architecture containing a dual-core ARM Cortex-A72 processor, a dual-core ARM Cortex-R5F processor, 1,968 DSPs, a customizable FPGA, and 400 standalone AIE tiles.

Data and Resources

Original MetadataJSON
The json representation of the dataset with its distributions based on DCAT.
Explore
- Preview
- Download

Cite this as

Jie Lei, José Flich, Enrique S. Quintana-Ortí (2025). Dataset: Versal VCK190 ACAP. https://doi.org/10.57702/32iyy9cr

DOI retrieved: January 2, 2025

Additional Info

Field	Value
Created	January 2, 2025
Last update	January 2, 2025
Defined In	https://doi.org/10.48550/arXiv.2302.07594
Author	Jie Lei
More Authors	José Flich Enrique S. Quintana-Ortí
Homepage	https://www.xilinx.com/products/versal/vck190.html